/*!
    \file    link32fa016bx_uart.h
    \brief   definitions for the UART

    \version 2023, V1.0.0, firmware for Link32FA016BX
*/


#ifndef LINK32FA016BX_UART_H
#define LINK32FA016BX_UART_H

#include "link32fa016bx.h"
#include "link32fa016bx_rcu.h"

LINK32FA013BX_BEGIN_DECLS

/* USARTx(x=0,1,2)/UARTx(x=3,4) definitions */
#define UART0                        UART0_BASE               /*!< UART0 base address */
#define UART1                        UART1_BASE               /*!< UART1 base address */

/* registers definitions */
#define UART_IS(uartx)                   REG32((uartx) + (0x00000000U))   /*!< UART interrupt status register */
#define UART_IE(uartx)                   REG32((uartx) + (0x00000004U))   /*!< UART interrupt enable register */
#define UART_IT(uartx)                   REG32((uartx) + (0x00000008U))   /*!< UART interrupt test   register */
#define UART_AT(uartx)                   REG32((uartx) + (0x0000000CU))   /*!< UART alert test register */
#define UART_CTL(uartx)                  REG32((uartx) + (0x00000010U))   /*!< UART control register */
#define UART_STAT(uartx)                 REG32((uartx) + (0x00000014U))   /*!< UART status register */
#define UART_RXD(uartx)                  REG32((uartx) + (0x00000018U))   /*!< UART read data register */
#define UART_TXD(uartx)                  REG32((uartx) + (0x0000001CU))   /*!< UART write data register */
#define UART_FIFO_CTL(uartx)             REG32((uartx) + (0x00000020U))   /*!< UART fifo control register */
#define UART_FIFO_STAT(uartx)            REG32((uartx) + (0x00000024U))   /*!< UART fifo status register */
#define UART_OVRD(uartx)                 REG32((uartx) + (0x00000028U))   /*!< UART override control register */
#define UART_OVSVAL(uartx)               REG32((uartx) + (0x0000002CU))   /*!< UART oversampled value register */
#define UART_TOCTL(uartx)                REG32((uartx) + (0x00000030U))   /*!< UART RX timeout control register */

/* bits definitions */
/* USARTx_INTR_STAT */
#define UART_IS_PERR_Pos           7                                 /*!< parity error position*/
#define UART_IS_PERR_Msk           BIT(7)                            /*!< parity error mask */
#define UART_IS_TMOUT_Pos          6                                 /*!< time out position */
#define UART_IS_TMOUT_Msk          BIT(1)                            /*!< time out mask */
#define UART_IS_BKERR_Pos          5                                 /*!< break condition error position */
#define UART_IS_BKERR_Msk          BIT(5)                            /*!< break condition error mask */
#define UART_IS_FERR_Pos           4                                 /*!< frame error position */
#define UART_IS_FERR_Msk           BIT(4)                            /*!< frame error mask */
#define UART_IS_RXOV_Pos           3                                 /*!< RX overflow position */
#define UART_IS_RXOV_Msk           BIT(3)                            /*!< RX overflow mask */
#define UART_IS_TXMT_Pos           2                                 /*!< TX empty position */
#define UART_IS_TXMT_Msk           BIT(2)                            /*!< TX empty mask */
#define UART_IS_RXWMK_Pos          1                                 /*!< RX watermark position */
#define UART_IS_RXWMK_Msk          BIT(1)                            /*!< RX watermark mask */
#define UART_IS_TXWMK_Pos          0                                 /*!< TX watermark position */
#define UART_IS_TXWMK_Msk          BIT(0)                            /*!< TX watermark mask */

/* USARTx_INTR_ENA */
#define UART_IE_PERR_Pos           7                                  /*!< parity error position */
#define UART_IE_PERR_Msk           BIT(7)                             /*!< parity error mask */
#define UART_IE_TMOUT_Pos          6                                  /*!< time out position */
#define UART_IE_TMOUT_Msk          BIT(1)                             /*!< time out mask */
#define UART_IE_BKERR_Pos          5                                  /*!< break condition error position */
#define UART_IE_BKERR_Msk          BIT(5)                             /*!< break condition error mask */
#define UART_IE_FERR_Pos           4                                  /*!< frame error position */
#define UART_IE_FERR_Msk           BIT(4)                             /*!< frame error mask */
#define UART_IE_RXOV_Pos           3                                  /*!< RX overflow position */
#define UART_IE_RXOV_Msk           BIT(3)                             /*!< RX overflow mask */
#define UART_IE_TXMT_Pos           2                                  /*!< TX empty position */
#define UART_IE_TXMT_Msk           BIT(2)                             /*!< TX empty mask */
#define UART_IE_RXWMK_Pos          1                                  /*!< RX watermark position */
#define UART_IE_RXWMK_Msk          BIT(1)                             /*!< RX watermark mask */
#define UART_IE_TXWMK_Pos          0                                  /*!< TX watermark position */
#define UART_IE_TXWMK_Msk          BIT(0)                             /*!< TX watermark mask */

/* USARTx_INTR_TEST */
#define UART_IT_PERR_Pos           7                                  /*!< parity error position */
#define UART_IT_PERR_Msk           BIT(7)                             /*!< parity error mask */
#define UART_IT_TMOUT_Pos          6                                  /*!< time out position */
#define UART_IT_TMOUT_Msk          BIT(1)                             /*!< time out mask */
#define UART_IT_BKERR_Pos          5                                  /*!< break condition error position */
#define UART_IT_BKERR_Msk          BIT(5)                             /*!< break condition error mask */
#define UART_IT_FERR_Pos           4                                  /*!< frame error position */
#define UART_IT_FERR_Msk           BIT(4)                             /*!< frame error mask */
#define UART_IT_RXOV_Pos           3                                  /*!< RX overflow position */
#define UART_IT_RXOV_Msk           BIT(3)                             /*!< RX overflow mask */
#define UART_IT_TXMT_Pos           2                                  /*!< TX empty position */
#define UART_IT_TXMT_Msk           BIT(2)                             /*!< TX empty mask */
#define UART_IT_RXWMK_Pos          1                                  /*!< RX watermark position */
#define UART_IT_RXWMK_Msk          BIT(1)                             /*!< RX watermark mask */
#define UART_IT_TXWMK_Pos          0                                  /*!< TX watermark position */
#define UART_IT_TXWMK_Msk          BIT(0)                             /*!< TX watermark mask */

#define UART_AT_FATAL_Pos          0                                  /*!< write 1 to trigger one alert event of this kind position */
#define UART_AT_FATAL_Msk          BIT(0)                             /*!< write 1 to trigger one alert event of this kind mask */

#define UART_CTL_NCO_Pos           16                                 /*!< BAUD clock rate control position */
#define UART_CTL_NCO_Msk           BITS(16,31)                        /*!< BAUD clock rate control mask */
#define UART_CTL_RXBLVL_Pos        8                                  /*!< Trigger level for RX break detection position */
#define UART_CTL_RXBLVL_Msk        BITS(8,9)                          /*!< Trigger level for RX break detection mask */
#define UART_CTL_PODD_Pos          7                                  /*!< 1 for odd parity, 0 for even parity position */
#define UART_CTL_PODD_Msk          BIT(7)                             /*!< 1 for odd parity, 0 for even parity mask */
#define UART_CTL_PEN_Pos           6                                  /*!< Parity is enabled position */
#define UART_CTL_PEN_Msk           BIT(6)                             /*!< Parity is enabled mask */
#define UART_CTL_LLPBK_Pos         5                                  /*!< Line loopback enable position */
#define UART_CTL_LLPBK_Msk         BIT(5)                             /*!< Line loopback enable mask */
#define UART_CTL_SLPBK_Pos         4                                  /*!< System loopback enable position */
#define UART_CTL_SLPBK_Msk         BIT(4)                             /*!< System loopback enable mask */
#define UART_CTL_NF_Pos            2                                  /*!< RX noise filter enable position */
#define UART_CTL_NF_Msk            BIT(2)                             /*!< RX noise filter enable mask */
#define UART_CTL_RX_Pos            1                                  /*!< RX enable position */
#define UART_CTL_RX_Msk            BIT(1)                             /*!< RX enable mask */
#define UART_CTL_TX_Pos            0                                  /*!< TX enable position */
#define UART_CTL_TX_Msk            BIT(0)                             /*!< TX enable mask */

#define UART_STAT_RXMT_Pos         5                                  /*!< RX Empty */
#define UART_STAT_RXMT_Msk         BIT(5)                             /*!< RX Empty */
#define UART_STAT_RXIDLE_Pos       4                                  /*!< RX Idle */
#define UART_STAT_RXIDLE_Msk       BIT(4)                             /*!< RX Idle */
#define UART_STAT_TXIDLE_Pos       3                                  /*!< TX Idle */
#define UART_STAT_TXIDLE_Msk       BIT(3)                             /*!< TX Idle */
#define UART_STAT_TXMT_Pos         2                                  /*!< TX Empty */
#define UART_STAT_TXMT_Msk         BIT(2)                             /*!< TX Empty */
#define UART_STAT_RXFU_Pos         1                                  /*!< RX Full */
#define UART_STAT_RXFU_Msk         BIT(1)                             /*!< RX Full */
#define UART_STAT_TXFU_Pos         0                                  /*!< TX Full */
#define UART_STAT_TXFU_Msk         BIT(0)                             /*!< TX Full */


/* UARTx_RX DATA */
#define UART_RXD_DATA_Pos          0                                 /*!<  Receive data value */
#define UART_RXD_DATA_Msk          BITS(0,8)                         /*!<  Receive data value */
/* UARTx_TX DATA */
#define UART_TXD_DATA_Pos          0                                 /*!<  Receive data value */
#define UART_TXD_DATA_Msk          BITS(0,8)                         /*!<  Receive data value */

#define UART_FIFO_CTL_TXILVL_Pos   5                                 /*!< Trigger level for RX interrupts */
#define UART_FIFO_CTL_TXILVL_Msk   BITS(5,7)                         /*!< Trigger level for RX interrupts */
#define UART_FIFO_CTL_RXILVL_Pos   2                                 /*!< Trigger level for RX interrupts */
#define UART_FIFO_CTL_RXILVL_Msk   BITS(2,4)                         /*!< Trigger level for RX interrupts */
#define UART_FIFO_CTL_TXRST_Pos    1                                 /*!< TX FIFO reset */
#define UART_FIFO_CTL_TXRST_Msk    BIT(1)                            /*!< TX FIFO reset */
#define UART_FIFO_CTL_RXRST_Pos    0                                 /*!< RX FIFO reset */
#define UART_FIFO_CTL_RXRST_Msk    BIT(0)                            /*!< RX FIFO reset */

#define UART_FIFO_STAT_RXLVL_Pos   16                                /*!< Current fill level of RX fifo */
#define UART_FIFO_STAT_RXLVL_Msk   BITS(16, 23)                      /*!< Current fill level of RX fifo */
#define UART_FIFO_STAT_TXLVL_Pos   0                                 /*!< Current fill level of TX fifo */
#define UART_FIFO_STAT_TXLVL_Msk   BITS(0,  16)                      /*!< Current fill level of TX fifo */

#define UART_OVRD_TXEN_Pos         0                                 /*!< Enable TX pin override control*/
#define UART_OVRD_TXEN_Msk         BIT(0)                            /*!< Enable TX pin override control*/
#define UART_OVRD_TXVAL_Pos        1                                 /*!< TX pin override value*/
#define UART_OVRD_TXVAL_Msk        BIT(1)                            /*!< TX pin override value*/

#define UART_OVSVAL_RX_Pos         0                                 /*!< Oversampled receive value */
#define UART_OVSVAL_RX_Msk         BITS(0,15)                        /*!< Oversampled receive value*/

#define UART_TOCTL_EN_Pos          0                                 /*!< UART RX timeout control enable */
#define UART_TOCTL_EN_Msk          BITS(0,23)                        /*!< UART RX timeout control enable */
#define UART_TOCTL_VAL_Pos         0                                 /*!< UART RX timeout control value */
#define UART_TOCTL_VAL_Msk         BITS(0,23)                        /*!< UART RX timeout control value */

/* UART transmitter configure */
#define CTL_TEN(regval)           (BIT(0) & ((uint32_t)(regval) << 0))
#define UART_TRANSMIT_ENABLE       CTL_TEN(1)                       /*!< enable transmitter */
#define UART_TRANSMIT_DISABLE      CTL_TEN(0)                       /*!< disable transmitter */

/* UART receiver configure */
#define CTL_REN(regval)           (BIT(1) & ((uint32_t)(regval) << 1))
#define UART_RECEIVE_ENABLE        CTL_REN(1)                       /*!< enable receiver */
#define UART_RECEIVE_DISABLE       CTL_REN(0)                       /*!< disable receiver */

/* UART noise filter */
#define CTL_NF(regval)            (BIT(2) & ((uint32_t)(regval) << 2))
#define UART_NF_ENABLE             CTL_NF(1)                        /*!< enable noise filter */
#define UART_NF_DISABLE            CTL_NF(0)                        /*!< disable noise filter */

/* UART System Loopback enable */
#define CTL_SLPBK(regval)         (BIT(4) & ((uint32_t)(regval) << 4))
#define UART_SLPBK_ENABLE          CTL_SLPBK(1)                     /*!< enable system loopback */
#define UART_SLPBK_DISABLE         CTL_SLPBK(0)                     /*!< disable system loopback */

/* UART Line Loopback enable */
#define CTL_LLPBK(regval)         (BIT(4) & ((uint32_t)(regval) << 4))
#define UART_LLPBK_ENABLE          CTL_LLPBK(1)                     /*!< enable line loopback */
#define UART_LLPBK_DISABLE         CTL_LLPBK(0)                     /*!< disable line loopback */

/* USART parity bits definitions */
#define CTL_PM(regval)            (BITS(6,7) & ((uint32_t)(regval) << 6))
#define UART_PM_NONE               CTL_PM(0)                        /*!< no parity */
#define UART_PM_EVEN               CTL_PM(1)                        /*!< even parity */
#define UART_PM_ODD                CTL_PM(3)                        /*!< odd parity */

#define CTL_RXBLVL(regval)        (BITS(8,9) & ((uint32_t)(regval) << 8))
#define UART_RXBLVL_2CHAR          CTL_RXBLVL(0)                    /*!< RX pin must be low at less 2  char times to detect break condition */
#define UART_RXBLVL_4CHAR          CTL_RXBLVL(1)                    /*!< RX pin must be low at less 4  char times to detect break condition */
#define UART_RXBLVL_8CHAR          CTL_RXBLVL(2)                    /*!< RX pin must be low at less 8  char times to detect break condition */
#define UART_RXBLVL_16CHAR         CTL_RXBLVL(3)                    /*!< RX pin must be low at less 16 char times to detect break condition */

#define CTL_NCO(regval)           (BITS(16,31) & ((uint32_t)(regval) << 16))

#define FIFO_CTL_RXRST(regval)    (BIT(0) & ((uint32_t)(regval) << 0))
#define UART_RXFIFO_RST_REQ        FIFO_CTL_RXRST(1)

#define FIFO_CTL_TXRST(regval)    (BIT(1) & ((uint32_t)(regval) << 1))
#define UART_TXFIFO_RST_REQ        FIFO_CTL_RXRST(1)

#define FIFO_CTL_RXILVL(regval)   (BITS(2,4) & ((uint32_t)(regval) << 2))
#define UART_RXWMK_1CHAR           FIFO_CTL_RXILVL(0)
#define UART_RXWMK_2CHAR           FIFO_CTL_RXILVL(1)
#define UART_RXWMK_4CHAR           FIFO_CTL_RXILVL(2)
#define UART_RXWMK_8CHAR           FIFO_CTL_RXILVL(3)
#define UART_RXWMK_16CHAR          FIFO_CTL_RXILVL(4)
#define UART_RXWMK_32CHAR          FIFO_CTL_RXILVL(5)
#define UART_RXWMK_64CHAR          FIFO_CTL_RXILVL(6)
#define UART_RXWMK_128CHAR         FIFO_CTL_RXILVL(7)

#define FIFO_CTL_TXILVL(regval)   (BITS(5,7) & ((uint32_t)(regval) << 5))
#define UART_TXWMK_1CHAR           FIFO_CTL_TXILVL(0)
#define UART_TXWMK_2CHAR           FIFO_CTL_TXILVL(1)
#define UART_TXWMK_4CHAR           FIFO_CTL_TXILVL(2)
#define UART_TXWMK_8CHAR           FIFO_CTL_TXILVL(3)
#define UART_TXWMK_16CHAR          FIFO_CTL_TXILVL(4)
#define UART_TXWMK_32CHAR          FIFO_CTL_TXILVL(5)
#define UART_TXWMK_64CHAR          FIFO_CTL_TXILVL(6)
#define UART_TXWMK_128CHAR         FIFO_CTL_TXILVL(7)




/* function declarations */
/* initialization functions */
/* reset UART */
void uart_deinit(uint32_t uart_periph);
/* configure UART baud rate value */
void uart_baudrate_set(uint32_t uart_periph, uint32_t baudval);
/* configure UART parity function */
void uart_parity_config(uint32_t uart_periph, uint32_t paritycfg);

/* UART normal mode communication */
/* enable UART */
void uart_enable(uint32_t uart_periph);
/* disable UART */
void uart_disable(uint32_t uart_periph);
/* configure UART transmitter */
void uart_transmit_config(uint32_t uart_periph, uint32_t txconfig);
/* configure UART receiver */
void uart_receive_config(uint32_t uart_periph, uint32_t rxconfig);
/* UART transmit data function */
void uart_data_transmit(uint32_t uart_periph, uint32_t data);
/* UART receive data function */
uint16_t uart_data_receive(uint32_t uart_periph);

void uart_break_detection_length_config(uint32_t uart_periph, uint32_t lblen);

void uart_pin_override_enable(uint32_t uart_periph);
void uart_pin_override_disable(uint32_t uart_periph);
void uart_pin_override_set(uint32_t uart_periph, uint32_t val);
/* send break frame */
void uart_send_break(uint32_t uart_periph);

LINK32FA016BX_END_DECLS

#endif /* LINK32FA016BX_UART_H */
